Computer systems are generally divided into a group of components. These components are typically driven by a system clock carrying a signal of a predetermined frequency. The system clock is distributed to the various components within the computer system to provide a timing reference. The phases of the clock signal are used for sequencing logic in integrated circuits, and is provided to various components in the computer system. Due to advanced silicon technology, modern microprocessors are capable of operating at much higher frequencies than other components within the computer system. In fact, in order to provide high performance computer systems, it is often advantageous to operate the microprocessor(s) at its highest possible frequency and other parts of the computer system at a lower frequency dictated by various technology constraints.
In many microprocessors clock signals are generated by a core clock. The core clock is typically synthesized as a multiple of the system clock by the use of a clock synthesizer (e.g., phased locked loop). The synthesizer multiplies the system clock by an N factor. The core clock is subsequently distributed throughout the microprocessor core. After a core clock signal is distributed, it is fed back to the clock synthesizer and divided by the same N factor in order to synchronize the core clock to the system clock. Therefore, various prior art microprocessors are capable of operating at an integer multiple of the frequency of the system clock, while other devices operate at the system clock frequency.
In such a computer system, synchronous data transfer between components operating at different frequencies is facilitated by the fact that a data transfer edge of the lower frequency clock corresponds to a data transfer edge of the higher frequency clock. For example, if a component is limited to 50 MHz operation, then microprocessors operating at 100, 150, 200, . . . MHz can be used in an integer multiple design. Therefore, the data transfer edge of the lower frequency clock (and/or corresponding data transfer edges of the higher frequency clock) can be used to cause synchronous data transfer.
Some prior art systems must generate more than a simple 1/N system clock to core ratio. Such prior art systems support 2/N ratios, where N may vary from 4 to 15. In the 2/N ratio scheme, N core clock cycles are generated for every two system clock cycles. Many 2/N ratio systems also use a ratioed clock. A ratioed clock is derived from the core clock by selecting specific edges of the core clock to generate the desired ratio. In order to generate the ratioed clock, enable signals must be generated for each cycle.
One problem with the prior art 2/N mode ratioed clock generation scheme is that a ratioed clock enable generation circuit must be designed for each particular ratio. Alternatively, additional circuitry must be provided for multiple ratio implementation.
Another problem with prior art systems is that ratioed clock enable signals are generated in a central location and must be globally routed across the microprocessor to each component of the system bus. Enable signals may switch at fairly high frequencies. High frequency switching signals that must be distributed along long global lines consume a considerable amount of power. In addition, routing long enable lines that switch at high frequencies may also couple noise into other signals that may be in close proximity to the enable signal. This phenomenon is typically referred to as crosstalk. Crosstalk may also occur when other signals couple noise into the enable signals, changing timing or inducing false enable pulses.
Therefore, a system and apparatus for generating and distributing ratioed clock enable signals for multiple integer ratio relationships is needed.